Paper Submission:
Submission Web Page: Under Construction
Paper submissions should be camera-ready manuscripts, not exceeding six two-column pages
(including a 50 to 200-word abstract, figures, tables, and bibliography) in pdf format.
The submission will be considered evidence that upon acceptance the author(s) will present the paper at the workshop.
The registration of at least one author is required for each presented paper; all presentations should be given in English.
Important Dates
Paper submission deadline: Under Construction, 2016
Notification of acceptance: Under Construction, 2016
Scope
Contributions related to electronic circuit and system testing are sought. Topics of interest include, but are not limited to:
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‧Test generation & fault simulation ‧Design for testability and reliability ‧Fault tolerance and error correction ‧Failure analysis & fault modeling ‧Analog/mixed-signal & RF testing ‧CPU testing ‧Memory testing and repair ‧High-speed I/O testing ‧System-level testing |
‧Built-in self-test ‧ESL testing ‧Silicon Debug and Diagnosis ‧Test economics ‧Wafer-level testing ‧SoC/SiP/3D IC testing ‧Interconnect testing and repair ‧On-chip monitoring ‧Yield and Reliability Enhancement |