Publications on "Timing-Aware Interconnect Testing, Diagnosis, Repair, and Monitoring for Multi-Die ICs"

´Á¥Z Journal Papers

  1. T.-Y. Li, S.-Y. Huang, H.-J. Hsu, C.-W. Tzeng, C.-T. Huang, J.-J. Liou, H.-P. Ma, P.-C. Huang, J.-C. Bor, C.-C. Tien, and M. Wang, and C.-W. Wu, "AC-Plus Scan Methodology for Small Delay Testing and Characterization," IEEE Trans. on VLSI Systems (TVLSI), Vol. 21, No. 2, pp. 329-341, (Feb. 2013).

  2. J.-W. You, S.-Y. Huang, Y.-H. Lin, M.-H. Tsai, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, "In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis," IEEE Trans. on VLSI Systems (TVLSI),  Vol. 21, No. 3, pp. 443-453, (March 2013).

  3. Y.-H. Lin, S.-Y. Huang, K.-H. Tsai, W.-T. Cheng, S. Sunter, Y.-F. Chou, and D.-M. Kwai, "Parametric Delay Test of Post-Bond TSVs in 3-D ICs via VOT Analysis", IEEE Trans. on Computer-Aided Design of Electronic Circuits (TCAD), Vol. 32, No. 5, pp.-737-747, (May 2013).

  4. S.-Y. Huang, Y.-H. Lin, Li-Ren Huang, K.-H. Tsai, and W.-T. Cheng, "Programmable Leakage Test and Binning for TSVs with Self-Timed Timing Control", IEEE Trans. on Computer-Aided Design of Electronic Circuits (TCAD), Vol. 32, No. 8, pp. 1265-1273, (Aug. 2013).

  5. L.-R. Huang, S.-Y. Huang, S. Sunter, K.-H. Tsai, and W.-T. Cheng "Oscillation-Based Pre-Bond TSV Test," IEEE Trans. on Computer-Aided Design of Electronic Circuits (TCAD). Vol. 32, No. 9, pp. 1440-1444, (Sept. 2013).

  6. L.-R. Huang, S.-Y. Huang, K.-H. (Hans) Tsai, and W.-T. Cheng, "Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs",  IEEE Trans. on Computer-Aided Design of Electronic Circuits (TCAD), Vol. 33, No. 3, pp. 476-488, (March 2014).

  7. C.-W. Tzeng, S.-Y. Huang, P.-Y. Chao, and R.-T. Ding, "Parameterized All-Digital PLL Architecture and Its Compiler to Support Easy Process Migration," IEEE Trans. on VLSI Systems (TVLSI), Vol. 22, No. 3, pp. 621-630, (March 2014).

  8. S.-Y. Huang, J.-Y. Lee, K.-H. (Hans) Tsai, and W.-T. Cheng, "Pulse-Vanishing Test for Interposers Wires in 2.5-D IC",  IEEE Trans. on Computer-Aided Design of Electronic Circuits (TCAD), Vol. 33, No. 8, pp. 1258-1268, (Aug. 2014).

  9. S.-Y. Huang and Li-Ren Huang, "PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning," IEEE Design and Test of Computers (D&T), Vol. 31, No. 4, pp. 36-42, (Aug. 2014).

  10. S.-Y. Huang, M.-T. Tsai, Z.-F. Zeng, K.-H. (Hans) Tsai, and W.-T. Cheng, "General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects," IEEE Trans. on Computer-Aided Design of Electronic Circuits (TCAD), (to appear).

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  1. J.-W. You, S.-Y. Huang, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, "Performance Characterization of TSV in 3D IC via Sensitivity Analysis," Proc. of Asian Test Symposium (ATS), pp. 389-394, (Dec. 2010).
  2. Y.-C. Chang, S.-Y. Huang, C.-W. Tzeng, "A Fully Cell-Based Design for Timing Measurement of Memory," Proc. of Int'l Conf. of Testing, (ITC), (Nov. 2011).
  3. Y.-H. Lin, S.-Y. Huang, K.-H. Tsai, W.-T. Cheng, S. Sunter, Y.-F. Chou, and D.-M. Kwai, "Small Delay Testing for TSVs in 3D ICs", Proc. of IEEE Design Automation Conf. (DAC), pp. 1031-1036, (June 2012).
  4. Y.-H. Lin, S.-Y. Huang, K.-H. Tsai, W.-T. Cheng, and S. Sunter, "A Unified Method for Parametric Fault Characterization of Post-Bond TSVs", Proc. of IEEE Int'l Test Conf. (ITC), Paper 12.1, pp. 1-10, (Nov. 2012).
  5. Y.-H. Lin, S.-Y. Huang,K.-H. Tsai, and W.-T. Cheng, "Programmable Leakage Test and Binning for TSVs", Proc. of IEEE Asian Test Symp. (ATS), pp. 43-48, (Nov. 2012).
  6. C.-H. Hsu, S.-Y. Huang, D.-M. Kwai, and Y.-F. Chou, "Worst-Case IR-Drop Monitoring with 1GHz Sampling Rate," Proc. of VLSI Design, Automation, and Test (VLSI-DAT),  (April 2013).
  7. S.-Y. Huang, J.-Y. Lee, K.-H. (Hans) Tsai, and W.-T. Cheng, "At-Speed BIST for Interposer Wires Supporting On-the-Spot Diagnosis", Int'l On-Line Test Symp. (IOLTS), pp. 67-72, (July 2013).
  8. S.-Y. Huang, L.-R. Huang, K.-H. (Hans) Tsai, and W.-T. Cheng, "Delay Testing and Characterization of Post-Bond Interposer Wires in 2.5-D ICs", Int'l Test Conf. (ITC), (Sept. 2013).¡@
  9. L.-R. Huang, S.-Y. Huang, K.-H. (Hans) Tsai, W.-T. Cheng, and S. Sunter, "Mid-Bond Interposer Wire Test", Int'l Asian Test Symp. (ATS), (Nov. 2013).¡@

  10. S.-Y. Huang, Z.-F. Zeng, K.-H. (Hans) Tsai, and W.-T. Cheng, "On-the-Fly Timing-Aware Built-In Self-Repair for High-Speed Interposer Wires in 2.5-D ICs",  Proc. of IEEE European Test Symp. (ETS), (May 2014).

  11. S.-Y. Huang, H.-X. Li, Z.-F. Zeng, K.-H. Tsai, and W.-T. Cheng, "On-Line Transition-Time Monitoring for Die-to-Die Interconnects in 3D ICs", Proc. of Asian Test Symp. (ATS), pp. 162-167, (Nov. 2014)

  12. S.-Y. Huang, M.-T. Tsai, K.-H. Tsai, and W.-T. Cheng, "Feedback-Bus Oscillation Ring: A General Architecture for Delay Characterization and Test of Interconnects", Proc. of Design, Automation, and Test in Europe (DATE), (March 2015).